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T8b949e# microReticulum native build — example runtime config.

T8b949e#

T8b949e# Copy this file to `rnoded.conf` and edit for your hardware.

T8b949e# Whichever directory you launch the binary from is searched first;

T8b949e# alternatively set the MR_CONFIG environment variable to a full path.

T8b949e#

T8b949e# Pin numbers semantics:

T8b949e# - On Linux native ([env:native], board = linux_hardware): each

T8b949e# pin_* value is interpreted as a BCM line number on the chip

T8b949e# identified by `gpio_chip` below. Use `gpioinfo gpiochip0` to

T8b949e# see what's available on your board. -1 disables a pin.

T8b949e# - On macOS native ([env:native-macos], board = cross_platform):

T8b949e# pin values are arbitrary sim-pin IDs in the range 0-63. They

T8b949e# don't reference real hardware; they just need to be unique

T8b949e# and within range. The values below are fine as-is for macOS.

T8b949e#

T8b949e# pin_sclk / pin_mosi / pin_miso / pin_cs are all owned by the spidev

T8b949e# kernel driver via the device tree and are never claimed by our libgpiod

T8b949e# bind step. spidev's SPI controller asserts hardware CS automatically

T8b949e# around each SPI_IOC_MESSAGE ioctl, and the SX127x driver now batches

T8b949e# address+data into a single ioctl so the chip sees one coherent command.

T8b949e# `pin_cs` is still listed here for documentation, but it's effectively

T8b949e# a Portduino sim pin — the modem driver's digitalWrite(_ss, ...) calls

T8b949e# are no-ops at the OS level, and that's the intended behavior.

T8b949e# ----- Storage / device paths -----

Te6edf3data_dir Tff7b72= Tb4b4b4.Tff7b72/Te6edf3state

Te6edf3spi_dev Tff7b72= Tff7b72/Te6edf3devTff7b72/Te6edf3spidev0T79c0ff.0

Te6edf3gpio_chip Tff7b72= Tff7b72/Te6edf3devTff7b72/Te6edf3gpiochip0

Te6edf3spi_speed_hz Tff7b72= T79c0ff2000000

T8b949e# ----- Pin map -----

T8b949e# Uncomment one of the board sections below and adjust as needed.

T8b949e# Keep the unused sections commented out (or delete them).

T8b949e# ----- Waveshare SX126x LoRa HAT for Raspberry Pi -----

T8b949e# modem = SX1262

T8b949e# pin_cs = 8 # BCM 8 (CE0) — Pi spidev owns this; libgpiod bind falls back, spidev auto-toggles CS

T8b949e# pin_reset = 22 # BCM 22

T8b949e# pin_busy = 23 # BCM 23

T8b949e# pin_dio = 24 # BCM 24 — DIO1

T8b949e# pin_rxen = -1

T8b949e# pin_txen = -1

T8b949e# pin_tcxo_enable = -1

T8b949e# pin_led_rx = -1

T8b949e# pin_led_tx = -1

T8b949e# ----- LuckFox Pico (Mini / Plus) + RFM95x LoRa module (SX1276) -----

T8b949e# Override the gpio_chip line at the top of this file to:

T8b949e# gpio_chip = /dev/gpiochip1

T8b949e# The pin values below are gpiochip1 line offsets — for the RV1103 /

T8b949e# RV1106 SoCs that's the kernel GPIO number minus 32 (e.g. GPIO1_D1 =

T8b949e# kernel 57 = line 25). The values are the same on both Pico Mini and

T8b949e# Pico Plus because they share the same SoC family; only the physical

T8b949e# header pin numbers differ between the two boards.

T8b949e# modem = SX1276

T8b949e# pin_cs = 16 # GPIO1_C0 — informational only; spidev owns CS, our digitalWrite is a sim no-op

T8b949e# pin_reset = 25 # GPIO1_D1

T8b949e# pin_busy = 22 # GPIO1_C6 — SX127x has no BUSY; harmless, the driver just pinMode(_, INPUT)

T8b949e# pin_dio = 23 # GPIO1_C7 — DIO0 (RFM95x G0; meshtasticd calls it IRQ)

T8b949e# pin_rxen = -1 # not used: RFM95x EN should be tied directly to 3V3

T8b949e# pin_txen = -1

T8b949e# pin_tcxo_enable = -1

T8b949e# pin_led_rx = -1

T8b949e# pin_led_tx = -1

T8b949e# Wiring note: tie the RFM95x EN pin to the LuckFox 3V3-OUT rail so the

T8b949e# module is always powered. Adafruit RFM95W breakouts have an onboard

T8b949e# regulator + level shifters; VIN can be 3.3 V or 5 V, but tying it to

T8b949e# 3V3-OUT keeps logic levels consistent with the SoC.

T8b949e# spi_dev / spi_speed_hz: keep /dev/spidev0.0 at 2_000_000 Hz (top of file).

T8b949e# ----- macOS sim defaults (the in-code defaults) -----

T8b949e# pin_cs = 0

T8b949e# pin_reset = 1

T8b949e# pin_busy = 2

T8b949e# pin_dio = 3

T8b949e# pin_rxen = 4

T8b949e# pin_txen = 5

T8b949e# pin_tcxo_enable = -1

T8b949e# pin_sclk = 6

T8b949e# pin_mosi = 7

T8b949e# pin_miso = 8

T8b949e# pin_led_rx = 9

T8b949e# pin_led_tx = 10

T8b949e# ----- LoRa radio settings -----

T8b949e# These get written into the EEPROM image on first boot. After that,

T8b949e# the values stored in ./eeprom are what's used (modify via the host

T8b949e# protocol or delete ./eeprom to re-seed from this file).

Te6edf3lora_freq_hz Tff7b72= T79c0ff915000000

Te6edf3lora_bw_hz Tff7b72= T79c0ff125000

Te6edf3lora_sf Tff7b72= T79c0ff8

Te6edf3lora_cr Tff7b72= T79c0ff5

Te6edf3lora_txp Tff7b72= T79c0ff17

T8b949e# ----- KISS host transport (TCP) -----

T8b949e# On native, the embedded firmware's USB-serial KISS channel is replaced

T8b949e# by a localhost TCP server. Tools that would normally open /dev/ttyACM0

T8b949e# (rnodeconf, RNS KISSInterface, etc.) connect to 127.0.0.1:<kiss_tcp_port>

T8b949e# instead. Single-client only; a second connection is rejected. Stale

T8b949e# clients are reaped after ~15 s of silence (plus TCP keepalive). Default

T8b949e# 7633 matches the ESP32 WiFi-remote port used in embedded builds.

Te6edf3kiss_tcp_port Tff7b72= T79c0ff7633

T8b949e# Expose the KISS server on all interfaces (0.0.0.0) instead of just

T8b949e# loopback. There is NO authentication or encryption on this socket —

T8b949e# only enable on networks you fully trust. Accepted boolean values

T8b949e# (case-insensitive): 1, true, yes, on / 0, false, no, off. Default: off.

Te6edf3kiss_tcp_public Tff7b72= Tff7b72false